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| IS61LV5128 512K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES * High-speed access times: 10, 12 and 15 ns * High-performance, low-power CMOS process * Multiple center power and ground pins for greater noise immunity * Easy memory expansion with CE and OE options * CE power-down * Fully static operation: no clock or refresh required * TTL compatible inputs and outputs * Single 3.3V power supply * Packages available: - 36-pin 400-mil SOJ - 36-pin miniBGA - 44-pin TSOP (Type II) ISSI (R) JULY 2001 DESCRIPTION The ISSI IS61LV5128 is a very high-speed, low power, 524,288-word by 8-bit CMOS static RAM. The IS61LV5128 is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 W (typical) with CMOS input levels. The IS61LV5128 operates from a single 3.3V power supply and all inputs are TTL-compatible. The IS61LV5128 is available in 36-pin 400-mil SOJ, 36pin mini BGA, and 44-pin TSOP (Type II) packages. FUNCTIONAL BLOCK DIAGRAM A0-A18 DECODER 512K X 8 MEMORY ARRAY VCC GND I/O DATA CIRCUIT I/O0-I/O7 COLUMN I/O CE OE WE CONTROL CIRCUIT ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 07/16/01 1 IS61LV5128 PIN CONFIGURATION 36 mini BGA 44-Pin TSOP (Type II) ISSI 2 3 4 5 6 (R) 1 A B C D E F G H A0 I/O4 I/O5 GND Vcc I/O6 I/O7 A9 A1 A2 NC WE NC A3 A4 A5 A6 A7 A8 I/O0 I/O1 Vcc GND A18 OE A10 CE A11 A17 A16 A12 A15 A13 I/O2 I/O3 A14 NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 GND Vcc I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC PIN DESCRIPTIONS A0-A18 CE OE WE I/O0-I/O7 Vcc GND NC Address Inputs Chip Enable Input Output Enable Input Write Enable Input Bidirectional Ports Power Ground No Connection 36-Pin SOJ A0 A1 A2 A3 A4 CE I/O0 I/O1 Vcc GND I/O2 I/O3 WE A5 A6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND Vcc I/O5 I/O4 A14 A13 A12 A11 A10 NC TRUTH TABLE Mode WE CE H L L L OE X H L X I/O Operation Vcc Current High-Z High-Z DOUT DIN ISB1, ISB2 ICC ICC ICC Not Selected X (Power-down) Output Disabled H Read H Write L A7 A8 A9 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 07/16/01 IS61LV5128 ISSI Value -0.5 to Vcc + 0.5 -55 to +125 -65 to +150 1.0 Unit V C C W (R) ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C 10 ns VCC 3.3V +10%, -5% 3.3V +10%, -5% 12 ns, 15 ns VCC 3.3V 10% 3.3V 10% CAPACITANCE(1,2) Symbol CIN CI/O Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 07/16/01 3 IS61LV5128 ISSI Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 -- 2.0 -0.3 GND VIN VCC GND VOUT VCC, Outputs Disabled Com. Ind. Com. Ind. -1 -5 -1 -5 Max. -- 0.4 VCC + 0.3 0.8 1 5 1 5 Unit V V V V A A (R) DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage (1) Note: 1. VIL = -3.0V for pulse width less than 10 ns. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ISB Vcc Operating Supply Current TTL Standby Current (TTL Inputs) TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX. VCC = Max., VIN = VIH or VIL CE VIH, f = fMAX. VCC = Max., VIN = VIH or VIL CE VIH, f = 0 VCC = Max., CE VCC - 0.2V, VIN VCC - 0.2V, or VIN 0.2V, f = 0 Com. Ind. Com. Ind. Com. Ind. Com. Ind. -10 ns Min. Max. -- -- -- -- -- -- -- -- 145 155 70 80 20 25 10 15 -12 ns Min. Max. -- -- -- -- -- -- -- -- 135 145 60 70 20 25 10 15 -15 ns Min. Max. -- -- -- -- -- -- -- -- 125 135 50 60 20 25 10 15 Unit mA mA ISB1 mA ISB2 mA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 07/16/01 IS61LV5128 READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time (2) (2) ISSI -10 ns Min. Max. 10 -- 3 -- -- 0 0 3 0 0 -- -- 10 -- 10 4 -- 4 -- 4 -- 10 -12 ns Min. Max. 12 -- 3 -- -- 0 0 3 0 0 -- -- 12 -- 12 5 -- 5 -- 6 -- 12 -15 ns Min. Max. 15 -- 3 -- -- 0 0 3 0 0 -- -- 15 -- 15 7 -- 6 -- 8 -- 15 Unit ns ns ns ns ns ns ns ns ns ns ns (R) tRC tAA tOHA tACE tDOE tLZOE tHZOE OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output Power Up Time Power Down Time tLZCE(2) tHZCE(2) tPU tPD Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 319 3.3V 3.3V 319 OUTPUT 30 pF Including jig and scope 353 OUTPUT 5 pF Including jig and scope 353 Figure 1 Figure 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 07/16/01 5 IS61LV5128 AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL) t RC ADDRESS ISSI (R) t AA t OHA DOUT PREVIOUS DATA VALID t OHA DATA VALID READ1.eps READ CYCLE NO. 2(1,3) (CE and OE Controlled) t RC ADDRESS t AA OE t OHA t DOE CE t HZOE t LZOE t ACE t LZCE t HZCE DATA VALID CE_RD2.eps DOUT HIGH-Z Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 07/16/01 IS61LV5128 WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Address Hold from Address Setup Time (4) ISSI -10 ns Min. Max. 10 8 8 0 0 8 10 6 0 0 0 -- -- -- Write End -- Write End -- -- -- -- -- 5 -- -12 ns Min. Max. 12 9 9 0 0 8 12 6 0 0 0 -- -- -- -- -- -- -- -- -- 6 -- -15 ns Min. Max. 15 10 10 0 0 10 12 7 0 0 0 -- -- -- -- -- -- -- -- -- 7 -- Unit ns ns ns ns ns ns ns ns ns ns ns (R) tWC tSCE tAW tHA tSA tPWE1 tPWE2 tSD tHD tHZWE tLZWE (2) (2) WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW) t WC ADDRESS VALID ADDRESS t SA CE t SCE t HA WE t AW t PWE1 t PWE2 t HZWE t LZWE HIGH-Z DOUT DATA UNDEFINED t SD DIN t HD DATAIN VALID CE_WR1.eps Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 07/16/01 7 IS61LV5128 WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle) t WC ADDRESS VALID ADDRESS ISSI (R) t HA OE CE LOW t AW t PWE1 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID CE_WR2.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE * VIH. WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) t WC ADDRESS VALID ADDRESS OE CE LOW t HA LOW t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE HIGH-Z t LZWE t SD DIN t HD DATAIN VALID CE_WR3.eps 8 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 07/16/01 IS61LV5128 ISSI Industrial Range: -40C to +85C Speed (ns) 10 10 10 12 12 12 15 15 15 Order Part No. IS61LV5128-10KI IS61LV5128-10TI IS61LV5128-10BI IS61LV5128-12KI IS61LV5128-12TI IS61LV5128-12BI IS61LV5128-15KI IS61LV5128-15TI IS61LV5128-15BI Package (R) ORDERING INFORMATION Commercial Range: 0C to +70C Speed (ns) 10 10 10 12 12 12 15 15 15 Order Part No. IS61LV5128-10K IS61LV5128-10T IS61LV5128-10B IS61LV5128-12K IS61LV5128-12T IS61LV5128-12B IS61LV5128-15K IS61LV5128-15T IS61LV5128-15B Package 400-mil Plastic SOJ TSOP (Type II) mini BGA (8mmx10mm) 400-mil Plastic SOJ TSOP (Type II) mini BGA (8mmx10mm) 400-mil Plastic SOJ TSOP (Type II) mini BGA (8mmx10mm) 400-mil Plastic SOJ TSOP (Type II) mini BGA (8mmx10mm) 400-mil Plastic SOJ TSOP (Type II) mini BGA (8mmx10mm) 400-mil Plastic SOJ TSOP (Type II) mini BGA (8mmx10mm) ISSI (R) Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. B 07/16/01 9 |
Price & Availability of IS61LV5128-10
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